The present disclosure relates to semiconductor structures, and more particularly to bipolar complementary metal-oxide-semiconductor (BiCMOS) integrated structures including a bipolar transistor having a self-aligned emitter, base, and collector, the base formed by selective epitaxy to bridge base regions.
In recent years, much effort has been directed toward perfecting a method of integrating bipolar and complementary metal oxide semiconductor (CMOS) technologies on a single wafer. The ability to combine CMOS with bipolar processes in a single (“BiCMOS”) process is extremely desirable for high performance circuits. For example, CMOS transistors are inherently low power devices with large noise margins that can achieve a high packing density. Meanwhile, bipolar transistors provide advantages in switching speed and current drive. Bipolar transistors are also characterized by high transconductance that is well suited for driving capacitive loads.
Besides the positive effect of enhancing the switching speed of the device, there are problems in that the changes in the collector of the bipolar transistor have some potentially negative side effects. One such problem is the increase of avalanche multiplication from the increased electric field in the collector-base space-charge region. A second problem is the increase of self-heating of the device. Such effects are described in more detail in G. Freeman, J.-S. Rieh, B. Jagannathan, Z. Yang, F. Guarin, A. Joseph, D. Ahigren, “SiGe HBT Performance and Reliability Trends through f.sub.T of 350 GHz,” Proc. IEEE Reliability Physics Symposium (Mar. 30, 2003) (hereinafter referred to as Freeman 2003) and M. Rickelt, H. M. Rein and, E. Rose, “Influence of Impact-Ionization Induced Instabilities on the Maximum Usable Output Voltage of Si-Bipolar Transistors,” IEEE Trans. on Electron Devices Vol. 48 n.4 p. 774-783 (April 2001) (hereinafter referred to as Rickelt 2001). One solution to the problem of the increasing self-heating of the device is to spread the current and thus the power over a larger region of the device, which reduces the thermal resistance and reduces the temperature rise of the device. Typically, as the current density of the device is increased due to the increased collector concentration, the width of the lithographically-defined emitter is reduced inversely with the current density increase, resulting in a similar current per unit length of the device.
One of the difficulties presented in integrating an MOS device with a bipolar device in the same circuit is that the fabrication steps required to form each of the separate devices often differ radically. That is, the steps used to fabricate a bipolar device are vastly different from the steps required to fabricate a CMOS or an MOS device.